1. Field of the Invention
The invention relates to a method for forming an alignment mark by utilizing a CMP (Chemical Mechanical Polishing) process.
2. Description of the Related Art
Conventionally, the manufacture of a semiconductor device includes repeated transfers of circuit patterns, which is formed on a mask, to a resist film formed on a Si-substrate.
In a lithographic process during the steps, a lithographic device detects a location of an alignment mark formed on the Si-substrate due to let the mask overlay the resist film accurately in a desired position. After, the mask is positioned in the desired position, a lithographic process is performed.
In recent years, a stepping projection aligner is used in a lithographic process because of requirements for shrinking the size of the semiconductor device. In FIGS. 4A and 4B, alignment marks 52a, which are used in a stepping projection aligner, are illustrated. The alignment marks 52a are formed in an alignment area of a Si-substrate 50. As the alignment marks 52a are formed with circuit patterns 52b simultaneously, the alignment marks 52a and the circuit patterns 52b have the same thickness. Then, an insulating layer 54 is formed on the entire surface of the Si-substrate 50, the circuit patterns 52b and the alignment marks 52a. It is difficult to detect the edges of the alignment marks 52a because the edges are covered by the insulating layer 54. However, a lithographic device can be used to detect edges 60, 61, 62, 63 surrounding the alignment marks in plan view of a step difference in the insulating layer 54 in order to align the mask. In particularly, the device detects light scattering diffracting at the edges 60, 61, 62, 63, which serve to define the location of the alignment mark.
A method of measuring the accuracy of overlay of the mask on the Si-substrate is explained below. A resist film is formed on the insulating layer 54. Then, a mask is aligned by detecting the edges 60, 61, 62, 63, and the resist film is exposed to the light through the mask. After the resist film is developed, a frame-shaped resist pattern 56, which surrounds the edges 60, 61, 62, is formed on the insulating layer 54, as shown in FIG. 4C. According to design, the distance Xa between the frame shaped pattern 56 and the edge 60 equals the distance Xb between the frame-shaped pattern 56 and the edge 61. Also, according to design, the distance Ya between the frame-shaped pattern 56 and the edge 62 equals the distance Yb between the frame-shaped pattern 56 and the edge 63. Therefore, the deviation in alignment of the mask in the horizontal direction is calculated as Xa-Xb, and the deviation in alignment of the mask in the vertical direction is calculated as Ya-Yb. If the result of the calculation is out of a range in which the circuit works satisfactorily, the lithographic process should be performed again. If the result of the calculation is in the range, the next process can be performed.
However, the step difference that appears in the insulating layer 54 sometimes causes a metalized wiring layer formed later in the circuit pattern area, to break when the semiconductor device is shrunk by reducing a distance between elements to be connected to each other by the metalized wiring layer. Therefore, as shown in FIG. 5, it is required that the surface of the insulating layer is planarized by a CMP (Chemical Mechanical Polishing) process. However, as the step difference caused by the alignment mark 52a is not appeared on the planarized surface of the insulating layer 54, a lithographic device cannot recognize the location of the edge of the alignment mark 52a when the metalized wiring layer is formed on the planarized surface of the insulating layer 54. Therefore, a mask can not be overlaid accurately over the semiconductor device in the desired location.